--
------------------------------------------------------------------
--
-- This code is form www.hendrikdettmer.de
--
-- Copyright by 
--
-- Hendrik Dettmer		(me@hendrikdettmer.de)
--
-- Have fun!
-- Questions? Just mail me!
-------------------------------------------------------------------
--


library ieee;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;

entity LFSRmain is
Generic (
	  sensebit : positive := 4 ;							--Indexplatz des Sensebits (wichtig beim A51)
			size : positive := 8 ;							--Größe des LFSR
			taps : STD_LOGIC_VECTOR := "01010101");	--Vektor für die Zuweisung der XORs
Port (	 rst : in STD_LOGIC;					
			 clk : in STD_LOGIC;
	 clkintern : in StD_LOGIC;
		  KorFn : in STD_LOGIC := '0';					--Wichtig nur für den A51
			seed : in STD_LOGIC_VECTOR(size-1 downto 0);	--Ursprungseingabe
	  senseout : out STD_LOGIC;							--SenseBit out für den A51
			out1 : out STD_LOGIC);
end LFSRmain;

architecture Behavioral of LFSRmain is

signal status : STD_LOGIC_VECTOR(size-1 downto 0);
signal xorvec : STD_LOGIC_VECTOR(size-1 downto 0);

begin
	
	
	gen1: for i in size-1 downto 0 generate
		max:if i = (size-1) generate
			xorvec(size-1) <= status(size-1) XOR KorFn;
		end generate;
		
		mid:if i < (size-1) generate
			one: if taps(i) = '1' generate
				xorvec(i) <= xorvec(i+1) xor status(i);
			end generate;
			nul: if taps(i) = '0' generate
				xorvec(i) <= xorvec(i+1);
			end generate;
		end generate;

	end generate;
	
	clkproc: process(clk, status,clkintern)
		begin
			senseout <= status(sensebit);
			out1 <= status(size-1);
			if clk'event and clk = '1' and clkintern = '1' then
					status(size-1 downto 0) <= status(size-2 downto 0) & xorvec(0);
					if rst = '1' then
						status <= seed;
					end if;
			end if;
	end process;
end Behavioral;